Advances in high speed VLSI circuits and optical transmission are making available broadband communication systems, such as broadband integrated services digital networks, B-ISDN. With regard to multiplexing and switching, the asynchronous transfer mode (ATM) is becoming a key technology for accommodating a wide range of services in B-ISDN. ATM switching is well adapted to transfer all kinds of digital information signals, using fixed-length cells (short packets) and asynchronous multiplexing. A cell consists of 53 octets (424 bits).
An ATM switch can be built using the ATOM (ATM output Buffer Modular) switch element. The ATOM switch element has an output-buffer architecture. The ATOM switch element uses a Lime-division multiplexed bus and first-in first-out (FIFO) buffers one for each individual output line. Since buffering is provided for outgoing lines, the switch architecture is called an output-buffer architecture.
The ATOM switch element is described in detail in the Proceedings of the IEEE Communications Society, "IEEE International Conference or Communications," pps 99-103, that was held on Jun. 11-14, 1989, as a paper entitled "Output-buffer Switch Architecture for Asynchronous Transfer Mode" by H. Suzuki, H. Nagano, T. Suzuki, T. Takeuchi, and S. Iwasaki.
For the very high speed systems that will be needed in the future, it is expected that it will be necessary to utilize a switch architecture that employs a number of such ATOM switch elements in parallel to handle multi-gigabits per second transmission speeds. In such a system, there need be included a number of distributors, a number of switch planes, and a number of resequencers.
However, in such a system involving a number of parallel switch planes there is a tendency for load unbalances to develop. That is, often some output buffers have to store a large number of cells while others have to store a small number of cells. This scenario leads to a large number of cell losses. If cell loss is to be kept low when the traffic peaks at particular switch planes, then considerable capacity must be provided in the output buffers, capacity that ay not be needed much of the time. To improve the performance of the system, it is desirable to make some provision for balancing the load better to minimize the total buffer capacity needed to be provided in the switch.
The present invention seeks to achieve a more uniform distribution of the load across all the switch planes of the system in order to keep the total number of cell loss to an acceptable level.